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Content
7
Preface
15
From the Old to the New
17
Acknowledgments
21
1 Verilog - A Tutorial Introduction
22
Getting Started
23
Behavioral Modeling of Combinational Circuits
32
Procedural Modeling of Clocked Sequential Circuits
35
Module Hierarchy
42
Summary
48
Exercises
49
2 Logic Synthesis
56
Overview of Synthesis
56
Combinational Logic Using Gates and Continuous Assign
58
Procedural Statements to Specify Combinational Logic
61
Inferring Sequential Elements
69
Inferring Tri-State Devices
73
Describing Finite State Machines
74
Finite State Machine and Datapath
79
Summary on Logic Synthesis
87
Exercises
89
3 Behavioral Modeling
94
Process Model
94
If-Then-Else
96
Loops
103
Multi-way Branching
107
Functions and Tasks
112
Rules of Scope and Hierarchical Names
123
Summary
127
Exercises
127
4 Concurrent Processes
130
Concurrent Processes
130
Events
132
The Wait Statement
137
A Concurrent Process Example
143
A Simple Pipelined Processor
149
Disabling Named Blocks
153
Intra-Assignment Control and Timing Events
155
Procedural Continuous Assignment
157
Sequential and Parallel Blocks
159
Exercises
161
5 Module Hierarchy
164
Module Instantiation and Port Specifications
164
Parameters
167
Arrays of Instances
171
Generate Blocks
172
Exercises
175
6 Logic Level Modeling
178
Introduction
178
Logic Gates and Nets
179
Continuous Assignment
192
A Mixed Behavioral/Structural Example
197
Logic Delay Modeling
201
Delay Paths Across a Module
208
Summary of Assignment Statements
210
Summary
211
Exercises
212
7 Cycle-Accurate Specification
216
Cycle-Accurate Behavioral Descriptions
216
Cycle-Accurate Specification
219
Mealy/Moore Machine Specifications
224
Introduction to Behavioral Synthesis
230
Summary
231
8 Advanced Timing
232
Verilog Timing Models
232
Basic Model of a Simulator
235
Non-Deterministic Behavior of the Simulation Algorithm
241
Non-Blocking Procedural Assignments
247
Summary
254
Exercises
255
9 User-Defined Primitives
260
Combinational Primitives
261
Sequential Primitives
264
Shorthand Notation
267
Mixed Level- and Edge-Sensitive Primitives
267
Summary
270
Exercises
270
10 Switch Level Modeling
272
A Dynamic MOS Shift Register Example
272
Switch Level Modeling
277
Ambiguous Strengths
284
The miniSim Example
291
Summary
302
Exercises
302
11 Projects
304
Modeling Power Dissipation
304
A Floppy Disk Controller
307
Tutorial Questions and Discussion
314
Structural Descriptions
314
Sequential Circuits
326
Lexical Conventions
330
White Space and Comments
330
Operators
331
Numbers
331
Strings
332
Identifiers, System Names, and Keywords
333
Verilog Operators
336
Table of Operators
336
2Operator Precedence
341
Operator Truth Tables
342
Expression Bit Lengths
343
Verilog Gate Types
344
Logic Gates
344
BUF and NOT Gates
346
BUFIF and NOTIF Gates
347
MOS Gates
348
Bidirectional Gates
349
CMOS Gates
349
Pullup and Pulldown Gates
349
Registers, Memories, Integers, and Time
350
Registers
350
Memories
351
Integers and Times
352
System Tasks and Functions
354
Display and Write Tasks
354
Continuous Monitoring
355
Strobed Monitoring
356
File Output
356
Simulation Time
357
Stop and Finish
357
Random
357
Reading Data From Disk Files
358
Formal Syntax Definition
360
Tutorial Guide to Formal Syntax Specification
360
Source text
364
Declarations
367
Primitive instances
372
Module and generated instantiation
374
UDP declaration and instantiation
375
Behavioral statements
376
Specify section
380
Expressions
386
General
391
Symbols
394
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