The Verillog® Hardware Description Language

Content

Preface

From the Old to the New

Acknowledgments

1 Verilog - A Tutorial Introduction

Getting Started

Behavioral Modeling of Combinational Circuits

Procedural Modeling of Clocked Sequential Circuits

Module Hierarchy

Summary

Exercises

2 Logic Synthesis

Overview of Synthesis

Combinational Logic Using Gates and Continuous Assign

Procedural Statements to Specify Combinational Logic

Inferring Sequential Elements

Inferring Tri-State Devices

Describing Finite State Machines

Finite State Machine and Datapath

Summary on Logic Synthesis

Exercises

3 Behavioral Modeling

Process Model

If-Then-Else

Loops

Multi-way Branching

Functions and Tasks

Rules of Scope and Hierarchical Names

Summary

Exercises

4 Concurrent Processes

Concurrent Processes

Events

The Wait Statement

A Concurrent Process Example

A Simple Pipelined Processor

Disabling Named Blocks

Intra-Assignment Control and Timing Events

Procedural Continuous Assignment

Sequential and Parallel Blocks

Exercises

5 Module Hierarchy

Module Instantiation and Port Specifications

Parameters

Arrays of Instances

Generate Blocks

Exercises

6 Logic Level Modeling

Introduction

Logic Gates and Nets

Continuous Assignment

A Mixed Behavioral/Structural Example

Logic Delay Modeling

Delay Paths Across a Module

Summary of Assignment Statements

Summary

Exercises

7 Cycle-Accurate Specification

Cycle-Accurate Behavioral Descriptions

Cycle-Accurate Specification

Mealy/Moore Machine Specifications

Introduction to Behavioral Synthesis

Summary

8 Advanced Timing

Verilog Timing Models

Basic Model of a Simulator

Non-Deterministic Behavior of the Simulation Algorithm

Non-Blocking Procedural Assignments

Summary

Exercises

9 User-Defined Primitives

Combinational Primitives

Sequential Primitives

Shorthand Notation

Mixed Level- and Edge-Sensitive Primitives

Summary

Exercises

10 Switch Level Modeling

A Dynamic MOS Shift Register Example

Switch Level Modeling

Ambiguous Strengths

The miniSim Example

Summary

Exercises

11 Projects

Modeling Power Dissipation

A Floppy Disk Controller

Tutorial Questions and Discussion

Structural Descriptions

Sequential Circuits

Lexical Conventions

White Space and Comments

Operators

Numbers

Strings

Identifiers, System Names, and Keywords

Verilog Operators

Table of Operators

2Operator Precedence

Operator Truth Tables

Expression Bit Lengths

Verilog Gate Types

Logic Gates

BUF and NOT Gates

BUFIF and NOTIF Gates

MOS Gates

Bidirectional Gates

CMOS Gates

Pullup and Pulldown Gates

Registers, Memories, Integers, and Time

Registers

Memories

Integers and Times

System Tasks and Functions

Display and Write Tasks

Continuous Monitoring

Strobed Monitoring

File Output

Simulation Time

Stop and Finish

Random

Reading Data From Disk Files

Formal Syntax Definition

Tutorial Guide to Formal Syntax Specification

Source text

Declarations

Primitive instances

Module and generated instantiation

UDP declaration and instantiation

Behavioral statements

Specify section

Expressions

General

Symbols

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