Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications

Foreword

Preface

Contents

Contributors

Part I Architectures

Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns

Introduction

HoneyComb Architecture

Architectural Considerations

HoneyComb Overview

Communication Network and Online Adaptive Routing Technique

Datapath Cells (DPHC)

Memory Cells (MEMHC)

Input/Output Cells (IOHC)

Power Saving Techniques

Tool Support

HoneyComb Assembler and the Hierarchical Programming Model

HoneyComb Language (HCL) and Compiler

Debugging Tool-HoneyComb Viewer

Super-Configuration Generator, Configuration Editor and Configuration Manager

Hierarchy Generator

Application and Synthesis Results

Future Work

Conclusion

References

Reconfigurable Components for Application-Specific Processor Architectures

Introduction

Parameterized eFPGA Target Architecture

Physical Implementation of Application Class Specific eFPGAs

Mapping and Configuration

Examples of (Stand Alone) eFPGAs as SoC Building Blocks

Examples of eFPGAs as Coprocessors to Standard RISC Processor Kernels

General-Purpose Processors Coupled with eFPGAs

ASIPs Coupled with eFPGA-Based Accelerators

ASIP

ASIP-eFPGA Coupling Mechanisms

Performance and Cost Evaluation

Examples of eFPGAs as Coprocessors to Application Specific Instruction Processors (rASIPs)

Conclusion

References

Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform

Introduction

Drawbacks of Existing Dynamically Reconfigurable Systems

The Erlangen Slot Machine

Architecture Overview

The BabyBoard

Computation and Reconfigurable Engine

The Reconfiguration Manager

Memory

Debug Lines

The MotherBoard

Inter-module Communication

Communication Between Adjacent Modules

Communication via Shared Memory

Communication via RMB

Communication via the Crossbar

Reconfiguration Manager

Flexible Plugin Architecture

Reconfiguration Scenarios

Implementation Results

Case Study: Video and Audio Streaming

Usage of the ESM in Different Fields

Conclusions

References

Part II Design Methods and Tools-Modeling, Evaluation and Compilation

Models and Algorithms for Hyperreconfigurable Hardware

Introduction

Hyperreconfigurable Machines

2-level Reconfiguration

Multi-level Reconfiguration

Heterogeneous Multi-level Reconfiguration

Example Architectures and Test Cases

Fine-granular Hyperreconfigurable Machine

Coarse-granular Hyperreconfigurable Machine

The Partition into Hypercontexts Problem

Experiments and Results

Diverse Granularity in Multi-level Reconfigurable Systems

Partial Reconfiguration and Hyperreconfiguration

Frame Model of Partially Reconfigurable Architectures

Results

Conclusions

References

Evaluation and Design Methods for Processor-Like Reconfigurable Architectures

Introduction

Benefits and Costs of Processor-Like Reconfiguration

CRC Model

Compiler

Evaluation

Specialization/Instruction Set Extension

Methodology

Study Case: Multipoint FFT for Scalable OFDMA Based Systems

Optimizing Power

Optimizing Power by Instruction Set Extensions

Optimizing Power by Dual-VDD Architectures

The Dual-VDD Architecture Model

Delay and Area

Power Estimation

Optimizing External Reconfiguration

Multi-Context Configuration Prefetching

Speculative Configuration Prefetching

Experimental Results

Conclusion

References

Adaptive Computing Systems and Their Design Tools

Introduction

Execution Model

ACS Architecture

Reconfigurable System-on-Chip Architecture

Operating System Integration

RCU-SPP Signalling

Shared Virtual Memory

Evaluation

Hardware/Software Co-compilation Flow

Overview

Profile-Based Inlining and Partitioning

CMDFG Intermediate Representation

CoCoMa Controller Model

Infrastructure

Parametrized Module Library

Physical Design Aspects

Reconfiguration Scheduling

Lessons Learned

Future Work

Conclusions

References

PolyDyn-Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs

Introduction

Related Work

Methodology

General Concept

Lifetime and Conflict Management

Derived Interface Classes

Modelling Example: Car Audio System

Coding Style: From C++ Polymorphism to OSSS+R

Devices and Timing

Simulation

Synthesising OSSS+R

From OSSS+R to RT Level

Recon-Object

Reconfiguration Controller

Method Calls

RTL Simulation Model

From RTL to Bitstreams

Evaluation

Conclusion and Future Work

References

Part III Design Methods and Tools-Optimization and Runtime Systems

Design Methods and Tools for Improved Partial Dynamic Reconfiguration

Introduction

Motivation

Reconfigurable Module Architecture and Partitioning

Reconfiguration State Graph

Module Mapping and Virtual Architecture

High-Level Synthesis of Reconfigurable Modules

Resource Type Binding

Resource Instance Binding

Control Generation

Experiments

Experimental Setup

Resource Type Binding Methods

Resource Instance Binding Methods

Implementation Scenarios

Benchmark Characteristics

Benchmark Results and Discussion

System Design for Efficient Partial Dynamic Reconfiguration

References

Dynamic Partial Reconfiguration by Means of Algorithmic Skeletons-A Case Study

Introduction

Overview of the Overall System

Library of Algorithmic Skeletons

Algorithmic Skeletons for Defining the Structure of the Design

Algoskels

Algorithmic Skeletons for Partial Reconfigurable Systems

Application Scenario: Channel Vocoder Analyzer

Conclusion

References

ReCoNodes-Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices

Introduction

Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device

Two-dimensional Strip Packing

Defragmentation Approach and Computational Results

Online Packing

Minimizing Communication Cost for Reconfigurable Slot Modules

Mathematical Model

Minimizing the Number of Parallel Segments

Minimize Segment-Constrained Bandwidth

Case Study and Results

No-break Dynamic Defragmentation of Reconfigurable Devices

Model and Problem Description

Problem Complexity and Moderate Densities

A Heuristic Method

Scheduling Dynamic Resource Requests

An ILP

Heuristic Methods

References

ReCoNets-Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections

Introduction

System Model

A Distributed Operating System Architecture for Networked Embedded Systems

Self-healing and Self-adaptiveness

Discrete Diffusion-Based Task Binding

Replica Placement

Hardware/Software Task Migration

Hardware/Software Morphing

Hardware/Software Checkpointing

Design and Synthesis of ReCoNets

Design Space Exploration

Dependability Analysis

Demonstrator

References

Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies

Introduction

Partial and Dynamic Reconfiguration

One-dimensional Dynamic and Partial Reconfigurable System Architecture

LUT Based Communication Primitives

Physically Realized Two-dimensional System Approach

Network on Chip

Router Base Modules for the On-line Placement

Switch for 2D Mesh Based NoC Approach

Switch Layout

Controlling the Switch

On Demand System Adaption

Physical on Line Routing of Communication Structures

Physical On-line Routing of Parameterizable Filter Modules

System Modelling

Tool Chain

Model Debugging

Problem

Debugging Flow

Interface and Architecture

Test

Conclusions

References

ReconOS: An Operating System for Dynamically Reconfigurable Hardware

Introduction

Related Work

Programming Model

Hardware Threads

Thread Creation and Termination

Run-Time System

Hardware Architecture

The Operating System Interface

Thread Supervision and Control

OS Call Relaying

Data Communication Routing

Hardware Multitasking

Software Architecture

Delegate Threads

Hardware Scheduler

Implementation

Target Platforms

Prototypes

ReconOS/eCos

ReconOS/Linux

Debugging and Monitoring

Experimental Measurements

Application Case Studies

Conclusion and Outlook

References

Part IV Applications

FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems

Introduction

Channel Codes

Convolutional Codes

Turbo Codes

LDPC Codes

Decoder Requirements

ASIP Design Methodologies

Architecture

General Considerations

Memory Concept

Pipeline

Dynamically Reconfigurable Channel Code Control

Instruction Set

ASIP Validation

Results

References

Dynamically Reconfigurable Systems for Wireless Sensor Networks

Introduction

Outline

Motivation and Background

Design of a Reconfigurable Function Unit

Functional Coverage of the RFU

The RFU Data Path

Dynamic Reconfiguration

Intra-task Reconfiguration

The Multi-context Configuration Table

Run Control via Tag-matching

Inter-task Reconfiguration

General System Architecture

Evaluation Results

Test Settings

Synthesis Results

Evaluation of Energy Efficiency

Reconfiguration Overhead

Comparison of Alternative Reconfiguration Mechanisms

Reconfiguration Power

Architecture Comparison

Prototyping of the Sensor Node System

Generalisation of the Results

Conclusion

References

DynaCORE-Dynamically Reconfigurable Coprocessor for Network Processors

Introduction

Network Processors

Requirements

System Architecture

Model

Principles of Theory

Modelling DynaCORE

Simulation

Runtime Adaptive Network-on-Chip

Architecture

Runtime Adaptation

Fault Tolerance

Reconfiguration Management

Basic Method

Optimised Approach

Technical Aspects

Evaluation

Summary

References

FlexPath NP-Flexible, Dynamically Reconfigurable Processing Paths in Network Processors

Introduction

FlexPath NP Concept

Application Dependent Path Decision

Load Dependent Path Decision

Formal Analysis

Simulative Exploration

FlexPath NP Architecture Evaluation

Load Balancing in FlexPath NP

FPGA Demonstrator

Architecture

Experiments

Demonstrator Setup

Single Data Plane CPU (Scenarios 1 and 2)

Two Data Plane CPUs (Scenarios 3 and 4)

AutoRoute (Scenario 5)

DynaCORE (Scenario 6)

Conclusion

References

AutoVision-Reconfigurable Hardware Acceleration for Video-Based Driver Assistance

Introduction

State of the Art & Related Work

Typical Scenario & Hardware Accelerators

AutoVision Architecture

The AddressEngine-A Pixel Processing Pipeline

Fast Dynamic Partial Reconfiguration

Motivation for Fast Reconfiguration

Inter Video Frame Reconfiguration

Intra Video Frame Reconfiguration

Bitstream Modification

Combitgen

Hardware Modification

ICAP Controller

Optimizing Throughput Through Modular Design

Bitstream Verification

Results

Performance of the Engines

Conclusion and Outlook

References

Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures

Introduction

Elliptic Curve Cryptography

Elliptic Curve Arithmetic

Finite Field Arithmetic

Karatsuba Multiplication

Multi-Segment-Karatsuba Multiplication

Enhanced Multi-Segment-Karatsuba Multiplication

Side Channel Attacks

Information Leaking of ECC Hardware Architectures

General Countermeasure Techniques

Countermeasure Through Reconfiguration

Securing ECC on Finite Field Arithmetic Level

Securing ECC on Elliptic Curve Arithmetic Level

DPA Experiments on Countermeasures

Resistance of the Secured eMSK-Multiplier

Conclusion and Future Work

References

Reconfigurable Controllers-A Mechatronic Systems Approach

Introduction

Design Methodology

Logical Controller Structure and Partitioning

Specification of Reconfigurable Controller Functionalities

Distributed Reconfiguration Control and Activation Strategies

Structure and Implementation

Structure and Components

Implementation and Target Hardware

Partial Reconfiguration Solution

Application

A Reconfigurable Controller for Piezo-Electric Actuators

Conclusion

References

Index