Analog Circuit Design - Smart Data Converters, Filters on Chip, Multimode Transmitters

Analog Circuit Design

Preface

Series on Integrated Circuits and Systems

Part I Smart Data Converters

1 LMS-Based Digital Assisting for Data Converters

1.1 Introduction

1.2 High-Resolution ADCs

1.3 Limits of ADC Resolution

1.4 Zero-Forcing LMS Algorithm

1.5 LMS-Based Calibration of the Pipelined ADC

1.5.1 Measurement Time and Dither Magnitude Constraints

1.5.2 Signal-Dependent Dithering Under Two Constraints

1.5.3 Linearity Improvement

1.5.4 Opamp Non-linearity Calibration

1.6 Noise Leakage Calibration in CT Cascaded Modulator

1.6.1 CT-to-DT Transform

1.6.2 Calibrated Cascaded Modulator

1.7 Conclusions

References

2 Pipelined ADC Digital Calibration Techniques and Tradeoffs

2.1 Introduction

2.2 Review of Error Sources in Pipelined ADCs

2.2.1 Gain Errors

2.2.2 DAC Errors

2.3 Digital Calibration Techniques

2.3.1 Digital Gain Error Calibration

2.3.2 DAC Gain Error Calibration

2.3.3 Foreground Calibration Techniques

2.3.4 Background Calibration

2.4 Rapid Background Calibration Techniques

2.4.1 Slow but Accurate Parallel ADC

2.4.2 Split-ADC Gain Error Calibration

2.4.3 Rapid DAC and Gain Error Correction

2.5 Using Digital Calibration to Build Low Power `Smart-ADCs'

2.5.1 Open Loop, Non-linear Gain Error Calibration

2.5.2 Capacitive Charge Pump Based Pipelined ADC

2.6 Summary

References

3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters

3.1 Introduction

3.2 Digital Calibration of Non-Linearity

3.2.1 DAC Non-linearity

3.2.2 Stage Gain Non-linearity

3.3 Range-Scaling in the First Pipeline Stage

3.3.1 Power Consumption in a Noise-Limited ADC

3.3.2 Circuit Implementation

3.4 SHA-Less Architecture

3.5 A 1.2V 14b 100MS/s ADC in 90nm CMOS

3.5.1 ADC Architecture

3.5.2 Measured Results

3.6 Conclusions

References

4 A Signal Processing View on Time-Interleaved ADCS

4.1 Introduction

4.2 Time-Interleaved ADCs

4.3 Modeling Time-Interleaved ADCs

4.4 Digital Calibration of Linear Channel Mismatches

4.4.1 Digital Correction Methods

4.4.1.1 Time Offset Mismatches

4.4.1.2 Frequency Response Mismatches

4.4.2 Digital Identification Methods

4.4.2.1 Off-line Identification

4.4.2.2 On-line Identification

4.5 Conclusions

References

5 DAC Correction and Flexibility, Classification, New Methods and Designs

5.1 Introduction

5.2 Correction Methods for Current-Steering DACs

5.2.1 Classification

5.2.2 New Correction Methods Based on Parallel Sub-DACs

5.2.2.1 New Method 1: High Level Mapping

5.2.2.2 New Method 2: Suppression of Harmonic Distortion

5.2.2.3 New Method 3: Self-Calibration of Binary Currents

5.3 Analysis of DAC Self-Calibration Methods

5.3.1 Self-Measurement Block

5.3.2 Algorithm Block

5.3.3 Self-Correction Block

5.4 Parallel Current-Steering DACs for Flexibility and Smartness

5.5 Design Examples and Measurements

5.5.1 Unary Currents Self-Calibration in a 12-bit 250nm DAC

5.5.2 Both Unary and Binary Currents Self-Calibration in a 12-bit 180nm Quad-Core Flexible DAC

5.6 Conclusions

References

6 Smart CMOS Current-Steering D/A-Converters for Embedded Applications

6.1 Introduction

6.2 A Multimode -DAC

6.3 A 13-b 200MS/s Background-Calibrated DAC

6.3.1 Converter Architecture

6.3.2 Segment Boundary Calibration

6.3.3 Randomization of the Calibration Period

6.3.4 Low-Bandwidth High-Resolution Mode

6.4 A 13-b 50MHz Bandwidth DAC with Active Output Stage

6.4.1 Converter Architecture

6.4.2 Direct Segment Calibration

6.5 Conclusions

References

Part II Filters On-Chip

7 Synthesis of Low-Sensitivity Analog Filters

7.1 Introduction

7.2 Passive Filters

7.2.1 Doubly Resistively Terminated Lossless Networks

7.2.2 Reflection Function

7.2.3 Sensitivity

7.2.4 Passband Sensitivity

7.3 Errors in the Elements in Doubly Terminated Filters

7.3.1 Errors in the Terminating Resistors

7.3.2 Effects of Lossy Elements

7.4 LC Filters with Diminishing Ripple

7.5 Approximations with Small Group Delay

7.6 Design of Doubly Terminated LC Filters

7.7 Conclusions

References

8 High-Performance Continuous-Time Filters with On-Chip Tuning

8.1 Introduction

8.2 Linear Operational Transconductance Amplifiers (OTAs)

8.2.1 Advanced Linearization Techniques

8.2.2 OTA Linearization Using Non-linear Elements

8.2.3 Design Example: A 30-MHz Elliptic Filter

8.3 Broadband Tuning for Interference Suppression in UWB Receivers

8.3.1 Analog LMS Control for Maximizing Attenuation

8.3.2 Interference Detection and Center Frequency Tuning

8.3.3 Experimental Results

8.4 Calibration of the Noise Transfer Function in a BP Modulator

8.5 Conclusion

References

9 Source-Follower-Based Continuous Time Analog Filters

9.1 Introduction

9.2 Source-Follower Circuit

9.3 A Source-Follower-Based Cascade CT Filter

9.3.1 Linearity Performance

9.3.2 Noise Performance

9.3.3 DC-Gain Loss

9.3.4 Minimum Supply Voltage

9.3.5 Silicon Prototype Experimental Results: A Fourth-Order Cascade SFB CT Filter for WLAN Receivers

9.4 A Source-Follower-Based Ladder CT Filter

9.4.1 Filter Circuital Topology

9.4.2 Minimum Supply Voltage

9.4.3 Silicon Prototype Experimental Results: A Sixth-Order Ladder SFB CT Filter for UWB Receivers

9.5 Conclusions

References

10 Reconfigurable Active-RC Filters with High Linearity and Low Noise for Home Networking Applications

10.1 Introduction

10.2 Architecture Selection

10.3 Architectural-Level Design Considerations

10.3.1 Optimized for Noise

10.3.2 Optimized for Speed

10.3.3 Optimized for Linearity

10.4 Circuit-Level Design Considerations

10.4.1 Reconfigurable Filter and Gain Stages

10.4.2 PGA Opamps with Adaptive Compensation

10.4.3 Tuning Loops

10.5 Experimental Results

10.6 Conclusions

References

11 On-Chip Instantaneously Companding Filters for Wireless Communications

11.1 Introduction

11.2 Companding Switched Capacitor Filter Implementation

11.3 Opamp's DC Offset Cancellation

11.4 WLAN Receiver Baseband Signal Chain

11.5 Simulation Results

11.6 Summary

References

12 BAW-IC CO-Integration Tunable Filters at GHz Frequencies

12.1 Introduction

12.2 BAW Technology

12.2.1 BAW Resonators

12.2.2 Electromechanical and Electrical Model of a BAW Resonator

12.3 BAW Resonator Filters

12.3.1 BAW Ladder Filters

12.3.2 BAW Lattice Filters

12.3.3 BAW Filters Synthesis Method

12.4 Tunable BAW Resonators

12.5 Design of an Electronically Tunable BAW Filter for Zero IF W-CDMA Receivers

12.5.1 BAW Tuning Cell Implementation

12.5.2 BAW Filter Implementation

12.5.3 BAW Filter Measurement Results

12.6 Tuning Circuitry for BAW Filters

12.6.1 Preliminary Discussion

12.6.2 Indirect Tuning Method I: PLL with a VCO as Master Cell

12.6.3 Indirect Tuning Method II: FLL with Envelope Detection

12.7 Design of a Digital Tuning Circuitry for a BAW Tunable Filter

12.7.1 Circuit Implementation

12.7.2 Measurement Results

12.8 Conclusions and Perspectives

References

Part III Multi-mode Transmitters

13 Multimode Transmitters: Easier with Strong Nonlinearity

13.1 Introduction

13.2 Architecture

13.3 Design Issues

13.4 Performance Measurements

13.5 Conclusions

References

14 RBS High Efficiency Power Amplifier Research – Challenges and Possibilities

14.1 Introduction

14.2 Power Amplifier Efficiency in an RBS Transmitter Context

14.3 Software Defined Radio (SDR) RBS

14.3.1 SDR RBS

14.4 Wide RF Bandwidth Power Amplifier Design

14.5 Efficiency Enhancement Techniques

14.5.1 Envelope Tracking Transmitter Architecture

14.5.2 Third Order Doherty

14.5.3 Pulsed Transmitter Architectures

14.5.3.1 Three Examples of Pulsed Transmitter Architectures

Baseband or Envelope PM

Cartesian PM

RF PM

14.5.3.2 Efficient Filtering of the Residual Quantization Distortion

14.6 Conclusions

References

15 Multi-Mode Transmitters in CMOS

15.1 Introduction

15.2 Direct Quadrature Voltage Modulator for Cellular Applications

15.2.1 Direct Quadrature Voltage Modulator

15.2.2 25% Duty-Cycle LO Generation

15.2.3 Measurement Results

15.3 Digital Polar Transmitter for Connectivity Applications

15.3.1 Direct Digital Polar Transmitter

15.3.2 Multi-phase Clocking

15.3.3 IC Implementation

15.3.4 Measurement Results

15.4 Conclusions

References

16 Challenges for Mobile Terminal CMOS Power Amplifiers

16.1 Introduction

16.2 Efficiency Improvement Techniques

16.3 Changing the RF Path

16.3.1 Discrete Class B

16.3.2 Power Combining

16.4 Changing the BB Path

16.4.1 Digital Polar

16.5 Conclusions

References

17 Multimode Transmitters with -Based All-Digital RF Signal Generation

17.1 Introduction

17.2 Modulation for All-Digital RF Signal Generation

17.2.1 What Can Modulation Bring in Integrated Transmitters?

17.2.2 IF DAC

17.2.3 1-bit RF DAC

17.2.4 Multi-bit RF DAC

17.3 Switched Power Amplification

17.3.1 Current and Voltage-Mode Switched Power Amplifier

17.3.2 Power Combining

17.4 Discussion on Digital and Mixed-Signal Blocks Implementation

17.4.1 Oversampling Up to RF Frequencies

17.4.2 Sampling Clock Synchronization on RF LO

17.4.3 Implementing the Modulator

17.4.3.1 Pipelined MASH Structures

17.4.3.2 High-Speed Modulator Implementation Using Redundant Representation

17.4.3.3 Going Further: Adaptive Placement of Complex Poles and Zeros of the NTF

17.4.4 Mixer and Digital-to-Analog Conversion

17.5 Dealing with Quantization Noise

17.5.1 BAW Filtering

17.5.2 RF Semi-Digital FIR Filtering

17.6 Conclusion

References

18 Switched Mode Transmitter Architectures

18.1 Introduction

18.2 Power Amplifiers

18.3 Envelope Modulation Techniques

18.4 Polar Switched Mode Architectures

18.5 Cartesian Switched Mode Architectures

18.6 RF Pulse Width Modulators

18.7 Delta-Sigma RF Pulse Width Modulation

18.8 Conclusions

References