Alpha AXP Architecture Reference Manual

Front Cover

Alpha Axp Architecture Reference Manual

Copyright Page

Table of Contents

FOREWORD

Preface to the First Edition

Preface to the Second Edition

Part 1: Common Architecture (I)

Chapter 1. Introduction (I)

1.1 The Alpha AXP Approach to RISC Architecture

1.2 Data Format Overview

1.3 Instruction Format Overview

1.4 Instruction Overview

1.5 Instruction Set Characteristics

1.6 Terminology and Conventions

Chapter 2. Basic Architecture (I)

2.1 Addressing

2.2 Data Types

2.3 Big-endian Addressing Support

Chapter 3. Instruction Formats (I)

3.1 Alpha AXP Registers

3.2 Notation

3.3 Instruction Formats

Chapter 4. Instruction Descriptions (I)

4.1 Instruction Set Overview

4.2 Memory Integer Load/Store Instructions

4.3 Control Instructions

4.4 Integer Arithmetic Instructions

4.5 Logical and Shift Instructions

4.6 Byte-Manipulation Instructions

4.7 Floating-Point Instructions

4.8 Memory Format Floating-Point Instructions

4.9 Branch Format Floating-Point Instructions

4.10 Floating-Point Operate Format Instructions

4.11 Miscellaneous Instructions

4.12 VAX Compatibility Instructions

Chapter 5. System Architecture and Programming Implications

5.1 Introduction

5.2 Physical Address Space Characteristics

5.3 Translation Buffers and Virtual Caches

5.4 Caches and Write Buffers

5.5 Data Sharing

5.6 Read/Write Ordering

5.7 Arithmetic Traps

Chapter 6. Common PALcode Architecture (I)

6.1 PALcode

6.2 PALcode Instructions and Functions

6.3 PALcode Environment

6.4 Special Functions Required for PALcode

6.5 PALcode Effects on System Code

6.6 PALcode Replacement

6.7 Required PALcode Instructions

Chapter 7. Console Subsystem Overview (I)

Chapter 8. Input/Output Overview (I)

Specific Operating System PALcode Architecture (II)

Part 2: OpenVMS AXP Software (ll–A)

Chapter 1. Introduction to OpenVMS AXP (II–A)

1.1 Register Usage

Chapter 2. OpenVMS AXP PALcode Instruction Descriptions (ll–A)

2.1 Unprivileged General OpenVMS AXP PALcode Instructions

2.2 OpenVMS AXP Queue Data Types

2.3 Unprivileged OpenVMS AXP Queue PALcode Instructions

2.4 Unprivileged VAX Compatibility PALcode Instructions

2.5 Unprivileged PALcode Thread Instructions

2.6 Privileged PALcode Instructions

Chapter 3. OpenVMS AXP Memory Management (II–A)

3.1 Introduction

3.2 Virtual Address Space

3.3 Physical Address Space

3.4 Memory Management Control

3.5 Page Table Entries

3.6 Memory Protection

3.7 Address Translation

3.8 Translation Buffer

3.9 Address Space Numbers

3.10 Memory Management Faults

Chapter 4. OpenVMS AXP Process Structure (II–A)

4.1 Process Definition

4.2 Hardware Privileged Process Context

4.3 Asynchronous System Traps (AST)

4.4 Process Context Switching

Chapter 5. OpenVMS AXP Internal Processor Registers (ll–A)

5.1 Internal Processor Registers

5.1 Internal Processor Registers

5.2 Stack Pointer Internal Processor Registers

5.3 IPR Summary

Chapter 6. OpenVMS AXP Exceptions, Interrupts, and Machine Checks (ll–A)

6.1 Introduction

6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame

6.3 Exceptions

6.4 Interrupts

6.5 Machine Checks

6.6 System Control Block

6.7 PALcode Support

Part 3: DEC OSF/1 Software (II–B)

Chapter 1. Introduction to DEC OSF/1 (II–B)

1.1 Programming Model

Chapter 2. DEC OSF/1 PALcode Instruction Descriptions (II–B)

2.1 Unprivileged PALcode Instructions

2.2 Privileged DEC OSF/1 PALcode Instructions

Chapter 3. DEC OSF/1 Memory Management (II–B)

3.1 Virtual Address Spaces

3.2 Physical Address Space

3.3 Memory Management Control

3.4 Page Table Entries

3.5 Memory Protection

3.6 Address Translation for Seg0 and Seg1

3.7 Translation Buffer

3.8 Address Space Numbers

3.9 Memory-Management Faults

Chapter 4. DEC OSF/1 Process Structure (II–B)

4.1 Process Definition

4.2 Process Control Block (PCB)

Chapter 5. DEC OSF/1 Exceptions and Interrupts (II–B)

5.1 Introduction

5.2 Processor Status

5.3 Stack Frames

5.4 System Entry Addresses

5.5 PALcode Support

Part 4: Windows NT AXP Software (ll–C)

Chapter 1. Introduction to Windows NT AXP Software (II–C)

1.1 Overview of System Components

1.2 Calling Standard Register Usage

1.3 Code Flow Conventions

Chapter 2. Processor, Process, and Thread Structures and Registers (II–C)

2.1 Processor Status

2.2 Internal Processor Register Summary

2.3 Internal Processor Registers

2.4 Processor Data Areas

2.5 Caches and Cache Coherency

2.6 Stacks

2.7 Processes and Threads

Chapter 3. Memory Management (II–C)

3.1 Virtual Address Space

3.2 I/O Space Address Extension

3.3 Canonical Virtual Address Format

3.4 Page Table Entries

3.5 Translation Buffer Management

3.6 Implications of Recursive TB Mapping

Chapter 4. Exceptions, Interrupts, and Machine Checks (ll–C)

4.1 Exceptions

4.2 Interrupts

4.3 Machine Checks

Chapter 5. Windows NT AXP PALcode Instruction Descriptions (ll–C)

5.1 Privileged PALcode Instructions

5.2 Unprivileged PALcode Instructions

5.3 Debug PALcode and Free PALcode

Chapter 6. Initialization and Firmware Transitions (II–C)

6.1 Initialization

6.2 Firmware Interfaces

Part 5: Console Interface Architecture (III)

Chapter 1. Console Subsystem Overview (III)

1.1 Console Implementations

1.2 Console Implementation Registry

1.3 Console Presentation Layer

1.4 Messages

1.5 Security

1.6 Internationalization

Chapter 2. Console Interface to Operating System Software (III)

2.1 Hardware Restart Parameter Block (HWRPB)

2.2 Environment Variables

2.3 Console Callback Routines

2.4 Interprocessor Console Communications

Chapter 3. System Bootstrapping (III)

3.1 Processor States and Modes

3.2 System Initialization

3.3 PALcode Loading and Switching

3.4 System Bootstrapping

3.5 System Restarts

3.6 Bootstrap Loading and Image Media Format

3.7 BB_WATCH

3.8 Implementation Considerations

Appendixes

Appendix A: Software Considerations

A.1 Hardware-Software Compact

A.2 Instruction-Stream Considerations

A.3 Data-Stream Considerations

A.4 Code Sequences

A.5 Timing Considerations: Atomic Sequences

Appendix B: IEEE Floating-Point Conformance

B.1 Alpha AXP Choices for IEEE Options

B.2 Alpha AXP Hardware Support of Software Exception Handlers

B.3 Mapping to IEEE Standard

Appendix C: Instruction Summary

C.1 Common Architecture Instruction Summary

C.2 IEEE Floating-Point Instructions

C.3 VAX Floating-Point Instructions

C.4 Opcode Summary

C.5 Common Architecture Opcodes in Numerical Order

C.6 OpenVMS AXP PALcode instruction Summary

C.7 DEC OSF/1 PALcode Instruction Summary

C.8 Windows NT AXP Instruction Summary

C.9 PALcode Opcodes in Numerical Order

C.10 Required PALcode Function Codes

C.11 Opcodes Reserved to PALcode

C.12 Opcodes Reserved to Digital

C.13 Unused Function Code Behavior

C.14 ASCII Character Set

Appendix D: Waivers and Implementation-Dependent Functionality

D.1 Waivers

D.2 Implementation-Specific Functionality

Index