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Foreword
5
Preface
7
Contents
9
List of Contributors
14
Parallel Transistor-Level Circuit Simulation
17
Introduction
18
Background
18
Parallelism Opportunities in Circuit Simulation
20
Parallel Netlist Parser
20
Parallel Approach for Nested Solver Loop
21
Device Evaluation
22
Linear Solvers for Circuit Simulation
23
Graph Mitigation using Multi-level Newton Methods
27
Multi-level Newton Method
27
Preserving Singleton Removal
28
Software
29
Parallel Linear Solver Strategy Comparison
31
Explanation of Tables
31
Numerical Results
32
Graph Mitigation Example
34
Conclusion
35
References
36
A Perspective on Fast-SPICE Simulation Technology
38
Introduction
38
SPICE: Transistor-Level Circuit Simulation
39
Usage and Limitations of SPICE
41
Need for Accelerated SPICE (`Fast-SPICE') Simulation
42
Fast-SPICE Technologies
42
SPICE vs. Fast-SPICE Techniques
42
Acceleration Technologies: Different Viewpoints
45
Examples of Fast-SPICE Technologies
48
Optimized Simulation of Parasitic Networks
48
Advanced Partitioning Technologies
49
Memory Simulation Acceleration
50
Challenges of Fast-SPICE and Future Research
54
References
57
Recent Advances in Structure-Preserving Model Order Reduction
58
Introduction
58
Description of RCL Networks
60
RCL Network Equations
60
RCL Transfer Functions
63
Passivity
64
Reciprocity
64
A Brief Review of Krylov Subspace-Based Model Order Reduction
65
Moment Matching and Padé Approximation
65
Reduced-Order Models
67
Moment Matching Via Krylov Subspace Methods
68
Passive Models Via Projection
71
Projection Combined with Krylov Subspaces
71
PRIMA
72
SPRIM
73
Preserving Block Structures
73
The Algorithm
74
Some Properties
76
Pros and Cons of PRIMA and SPRIM
76
Thick-Restart Krylov Subspace Techniques
78
Complex Expansion Points
81
Concluding Remarks
83
References
84
Injection Locking Analysis and Simulation of Weakly Coupled Oscillator Networks
86
Introduction
86
Oscillators
88
PPV/PRC Phase Macromodel of Single Oscillator
89
Malkin's Theorem
90
Injection Locking
91
Adler's Equation
92
Generalized Adler's Equation
92
Injection Locking Range of Ring Oscillator
94
Injection Locking Range of Hodgkin-Huxley Neuron
96
Coupled Oscillator Network Simulation
98
Coupled Oscillator Network Transient Simulation
98
Finding Oscillator Phases in the Synchronized State of a CON Numerically
99
PPV based Simulation of Ring Oscillator and Neuronal Oscillator Network
102
Conclusions
107
References
107
Dynamic Stability of Static Memories: Concepts and Advanced Numerical Analysis Techniques
109
Introduction
109
Static Noise Margins
110
Dynamic Stability Boundaries of Bistable Systems
111
Dynamic Noise Margins
113
Dynamic Read Noise Margin (DRNM)
113
Dynamic Write Noise Margin (DWNM)
115
Dynamic Hold Noise Margin (DHNM)
116
Relations to Conventional Static Noise Margins
117
Analysis of Dynamic Noise Margins
117
Computationally Efficient Tracing of Separatrices
118
Illustrative Examples
120
Numerical Stability of Separatrix Tracing
123
Extension to Memory Cells Modeled as High-Dimensional Systems
125
Conclusions
126
References
127
Recycling Circuit Simulation Techniques for Mass-Action Biochemical Kinetics
128
Introduction
129
Illustrative Examples
129
Circuit Equations
130
MAK Equations
131
Leakage and Degradation
133
System Comparisons
134
Circuit Case
134
MAK Case
135
Conservation Constraints
136
The Non-negative Orthant
140
Examples
143
Exploiting the Kronecker Form
143
Oscillator Sensitivity Analysis
145
Conclusions
147
References
148
Circuit-Based Models of Biomolecular System Dynamics
150
Capturing the Dynamics of Living Circuits
150
BioXyce: An Electrical Circuit-Based Systems Biology Simulation Platform
152
Modeling Biological Pathways Using BioXyce
153
Simulating Metabolic Processes with Genetic Control
155
Tryptophan Biosynthesis
155
Simulating the Tryptophan Hybrid Network
157
Boolean Kinetics Framework for Simulating Large Scale Gene Networks
160
Modeling Gene Networks with Boolean Logic
161
Using a Boolean Kinetics Model of Gene Regulationin the Tryptophan Hybrid Network
162
Simulation of Whole-Cell Inferred Gene Network
163
Signal Transduction Cascades
165
References
168
Analog Verification
170
Analog Verification
170
Design Time Line
178
Incomplete Implementation of the Methodology
179
Analog Verification Engineers
180
Adoption
181
Examples
182
Audio Codec
182
Micro-Controller Based Power Management Unit
183
RF Transceiver
183
SerDes
183
Conclusion
183
References
184
Formal Methods for Verification of Analog Circuits
185
Introduction
185
The Need for Formal Methods
186
Overview over Formalized Analog Verification Methods
188
Analog Model Checking
188
Analog Equivalence Checking
190
Formalizing the Verification Flow
190
Unifying and Formalizing Analog Verification Methodologies
191
Discrete State Space Modeling
191
Verification of Analog System Properties Using the Analog Specification Language (ASL)
193
Applying ASL Verification Algorithms to Transient Simulation Waveforms
195
Counterexample Generation
196
Complete State Space-Covering Input Stimuli Generation
197
Equivalence Checking Methodology Using Complete State Space-Covering Input Stimuli
198
The Verification Flow Perspective
199
Experimental Results
201
Conclusions
203
References
203
Index
205
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