Microprocessor Architectures - RISC, CISC and DSP

Front Cover

Microprocessor Architectures RISC, CISC and DSP

Copyright Page

Table of Contents

Preface

Acknowledgements

Chapter 1. Complex instruction set computers

8 bit microprocessors: the precursors of CISC

8 bit microprocessor register models

Requirements for a new processor architecture

Software compatibility

Enter the MC68000

Complex instructions, microcode and nanocode

The MC68000 hardware

Typical system

Multitasking operating systems

Context switching, task tables and kernels

Start of a revolution

The MC68010 virtual memory processor

Virtual memory support

Virtual machine support

MC68010 SUPERVISOR resource

Other improvements

The MC68008

The story continues

Chapter 2. 32 bit CISC processors

Enter HCMOS technology

Architectural challenges

The MC68020 32 bit performance standard

The internal design philosophy

The programmer's model

Dynamic bus sizing

On chip instruction cache

Debugging support

Coprocessor interface

MC68881 and MC68882 floating point coprocessors

The MC68651 paged memory management unit (PMMU)

The MC68030: the first commercial 50 MHz processor

Memory management

Chapter 3. The RISC challenge

The 80/20 rule

The initial RISC research

The Berkeley model

The Stanford model

The catalysts

The M88000 family

M88000 concurrent functional units

Multiple execution units and optimisation

Scoreboarding

Delayed branching

The MC88100 programming model

Handling exceptions

The MC88100 instruction set

Addressing data

Fetching data

MC88100 external functions

Single-cycle memory buses

MC88200 cache MMU

Memory management functions

Cache coherency

The MBUS protocol

M88000 master / checker fault tolerance

Future enhancements

Chapter 4. RISC wars

RISC versus CISC

Enter the MC68040

Superscalar alternatives

Superpipelining

Very long instruction word

Superscalar principles

Controlling multiple instructions per clock

Software control

The MC88110

Enter the PowerPC

The PowerPC architectural model

Execution pipelines

Branch delays

Branch folding

Static branch prediction

Branch prediction cache

Register renaming

The MPC601 block diagram

The MPC603 block diagram

Chapter 5. Digital signal processors

Processor requirements

The DSP56000 family

Basic architecture

The programming model

The instruction set

Arithmetic and logical instructions

Bit manipulation

Loop control

MOVE commands

Program control

Instruction format

Using special addressing and loop modes

Internal parallelism

Architectural differences

DSP96000 — combining integration and performance

OnCE — a new approach to emulation

Chapter 6. Memory, memory management and caches

Achieving processor throughput

Partitioning the system

Shadow RAM

DRAM versus SRAM

Optimising the DRAM interface

Page mode operation

Page interleaving

Alternative memory systems

Burst mode SRAM

Big vs. little endian organization

Memory management

Disadvantages of memory management

Segmentation and paging

Multitasking and user / supervisor conflicts

Table walking and RISC architectures

Instruction continuation versus restart

Memory management and DSP

Cache memory

Cache size and organization

Optimising line length and cache size

Logical versus physical caches

Unified versus Harvard caches

Cache coherency

Case 1: write through

Case 2: write back

Case 3: no caching of write cycles

Case 4: write buffer

Bus snooping

The MESI protocol

The MEI protocol

Streaming and CWF (critical word first)

Cache control instructions

Implementing memory systems

Secondary or level 2 caches

Conclusions

Chapter 7. Real-time software, interrupts and exceptions

What is real-time software

Responding to an interrupt

Improving performance

Interrupting CISC and RISC processors

RISC interrupt service routines

Improving software performance

Addressing data

Fetching data

Testing data

Saving and restoring register sets

Interrupting the DSP56000

Diadic versus triadic instruction sets

Instruction restart versus instruction continuation

External memory and real-time performance

Register windowing

Combining architectures

The M68300 family

Software considerations

Combining DSP processors

Conclusions

Chapter 8. Multiprocessing

SISD — single instruction, single data

SIMD — single instruction, multiple data

MIMD — multiple instruction, multiple data

MISD — multiple instruction, single data

Constructing a MIMD architecture

Processor bandwidths

Profiling

Cost of memory access

Fault tolerant systems

Single- and multiple-threaded operating systems

Chapter 9. Application examples

MC68020 and MC68030 design techniques for high reliability applications

Upgrading 8 bit systems

Transparent update techniques for digital filters using the DSP56000

Motor and servo control

Improved SRAM interfaces

Chapter 10. Semiconductor technology

Silicon technology

CMOS and bipolar technology

Fabrication technology

Packaging

Processor technology

Memory technology

Science fiction or not

Chapter 11. The changing design cycle

The shortening design cycle

The double-edged sword of technology

Make versus buy

Simulation versus emulation

Chapter 12. The next generations

MC68000 — superscalar CISC

The MPC604

The future for CISC

An alternative direction — system integration

The M68300 family

Improving the instruction set

Summary

Chapter 13. Selecting a micro-processor architecture

Meeting performance needs

Choice of platforms

Anticipating future needs

Software support

Development support

Standards

Built-in obsolescence

Market changes

Considering all the options

Appendices

A 'Lies, damn lies and benchmarks'

B Alternative micro-processor architectures

Index