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Front Cover
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Microprocessor Architectures RISC, CISC and DSP
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Copyright Page
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Table of Contents
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Preface
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Acknowledgements
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Chapter 1. Complex instruction set computers
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8 bit microprocessors: the precursors of CISC
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8 bit microprocessor register models
20
Requirements for a new processor architecture
26
Software compatibility
27
Enter the MC68000
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Complex instructions, microcode and nanocode
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The MC68000 hardware
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Typical system
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Multitasking operating systems
49
Context switching, task tables and kernels
51
Start of a revolution
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The MC68010 virtual memory processor
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Virtual memory support
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Virtual machine support
59
MC68010 SUPERVISOR resource
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Other improvements
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The MC68008
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The story continues
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Chapter 2. 32 bit CISC processors
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Enter HCMOS technology
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Architectural challenges
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The MC68020 32 bit performance standard
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The internal design philosophy
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The programmer's model
70
Dynamic bus sizing
74
On chip instruction cache
76
Debugging support
80
Coprocessor interface
82
MC68881 and MC68882 floating point coprocessors
84
The MC68651 paged memory management unit (PMMU)
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The MC68030: the first commercial 50 MHz processor
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Memory management
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Chapter 3. The RISC challenge
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The 80/20 rule
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The initial RISC research
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The Berkeley model
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The Stanford model
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The catalysts
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The M88000 family
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M88000 concurrent functional units
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Multiple execution units and optimisation
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Scoreboarding
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Delayed branching
105
The MC88100 programming model
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Handling exceptions
107
The MC88100 instruction set
108
Addressing data
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Fetching data
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MC88100 external functions
111
Single-cycle memory buses
113
MC88200 cache MMU
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Memory management functions
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Cache coherency
116
The MBUS protocol
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M88000 master / checker fault tolerance
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Future enhancements
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Chapter 4. RISC wars
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RISC versus CISC
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Enter the MC68040
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Superscalar alternatives
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Superpipelining
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Very long instruction word
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Superscalar principles
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Controlling multiple instructions per clock
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Software control
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The MC88110
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Enter the PowerPC
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The PowerPC architectural model
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Execution pipelines
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Branch delays
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Branch folding
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Static branch prediction
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Branch prediction cache
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Register renaming
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The MPC601 block diagram
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The MPC603 block diagram
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Chapter 5. Digital signal processors
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Processor requirements
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The DSP56000 family
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Basic architecture
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The programming model
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The instruction set
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Arithmetic and logical instructions
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Bit manipulation
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Loop control
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MOVE commands
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Program control
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Instruction format
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Using special addressing and loop modes
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Internal parallelism
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Architectural differences
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DSP96000 — combining integration and performance
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OnCE — a new approach to emulation
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Chapter 6. Memory, memory management and caches
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Achieving processor throughput
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Partitioning the system
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Shadow RAM
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DRAM versus SRAM
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Optimising the DRAM interface
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Page mode operation
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Page interleaving
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Alternative memory systems
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Burst mode SRAM
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Big vs. little endian organization
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Memory management
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Disadvantages of memory management
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Segmentation and paging
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Multitasking and user / supervisor conflicts
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Table walking and RISC architectures
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Instruction continuation versus restart
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Memory management and DSP
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Cache memory
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Cache size and organization
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Optimising line length and cache size
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Logical versus physical caches
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Unified versus Harvard caches
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Cache coherency
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Case 1: write through
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Case 2: write back
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Case 3: no caching of write cycles
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Case 4: write buffer
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Bus snooping
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The MESI protocol
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The MEI protocol
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Streaming and CWF (critical word first)
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Cache control instructions
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Implementing memory systems
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Secondary or level 2 caches
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Conclusions
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Chapter 7. Real-time software, interrupts and exceptions
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What is real-time software
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Responding to an interrupt
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Improving performance
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Interrupting CISC and RISC processors
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RISC interrupt service routines
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Improving software performance
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Addressing data
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Fetching data
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Testing data
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Saving and restoring register sets
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Interrupting the DSP56000
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Diadic versus triadic instruction sets
253
Instruction restart versus instruction continuation
254
External memory and real-time performance
254
Register windowing
256
Combining architectures
256
The M68300 family
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Software considerations
260
Combining DSP processors
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Conclusions
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Chapter 8. Multiprocessing
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SISD — single instruction, single data
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SIMD — single instruction, multiple data
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MIMD — multiple instruction, multiple data
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MISD — multiple instruction, single data
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Constructing a MIMD architecture
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Processor bandwidths
270
Profiling
271
Cost of memory access
272
Fault tolerant systems
275
Single- and multiple-threaded operating systems
278
Chapter 9. Application examples
281
MC68020 and MC68030 design techniques for high reliability applications
281
Upgrading 8 bit systems
291
Transparent update techniques for digital filters using the DSP56000
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Motor and servo control
299
Improved SRAM interfaces
305
Chapter 10. Semiconductor technology
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Silicon technology
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CMOS and bipolar technology
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Fabrication technology
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Packaging
317
Processor technology
320
Memory technology
320
Science fiction or not
322
Chapter 11. The changing design cycle
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The shortening design cycle
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The double-edged sword of technology
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Make versus buy
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Simulation versus emulation
331
Chapter 12. The next generations
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MC68000 — superscalar CISC
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The MPC604
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The future for CISC
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An alternative direction — system integration
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The M68300 family
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Improving the instruction set
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Summary
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Chapter 13. Selecting a micro-processor architecture
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Meeting performance needs
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Choice of platforms
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Anticipating future needs
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Software support
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Development support
357
Standards
360
Built-in obsolescence
361
Market changes
361
Considering all the options
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Appendices
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A 'Lies, damn lies and benchmarks'
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B Alternative micro-processor architectures
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Index
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